| TECHNICAL SESSIONS PROGRAM AGENDA | ||||
| Session1, Day 1 (January 5, 2015) 2.45 PM to 3.45 PM | ||||
Track A ROYAL BALLROOM |
Track B JAMAVAR(GROUND FLOOR) |
Track C KAMAL |
Track D GRAND BALLROOM |
Track E DIYA |
Session A1: Embedded Systems |
Session B1: Design Verification Chair: Anand Venkatachalam, Sandisk |
Session C1: Analog Chair: Murtuza Lilamwala, Cypress |
Session D1: IOT Chair: Nagaraj V Dixit, TI |
Session E1: User Design Chair: Sandeep Bhatia, Broadcom |
A1.1 ARGUS: A Framework for Rapid Design and Prototype of Heterogeneous Multicore Systems in FPGA Jude Angelo Ambrose, Tuo Li, Daniel Murphy, Shivam Gargg, Nick Higgins and Sri Parameswaran, UNSW |
B1.1 On-The-Fly Donut Formation in Compiled Memory Darvinder singh, Isha Garg, Vineet Sachan and Prasanna Nalawar, AMD & Synopsys |
C1.1 On Slew Rate Enhancement in Class-A Opamps Using Local Common-Mode Feedback Rakshitdatta K. S and Nagendra Krishnapura |
D1.1 Invited Talk: Environmental Pollution Monitoring : Gas Sensors to System Integration Navakanta Bhat, Indian Institute of Science |
E1.1: Invited Talk - Wearable Device For Physical and Emotional Health Monitoring Dr. Srinivasan Murali, CEO, SmartCardia |
| A1.2 Parameterizable FPGA framework for particle filter based object tracking in video Pinal Kumar Engineer, Velmurugan Rajbabu and Sachin Patkar, IIT Bombay |
B1.2 Scaling the uvm_reg model towards automation and simplicity of use Abhishek Jain and Richa Gupta |
C1.2 Accurate Constant Transconductance Generation Without Off-chip Components Imon Mondal and Nagendra Krishnapura |
D1.2 Towards a Real-Time Smart Water Monitoring System Vignesh Kudva, Prashanth Nayak, Bharadwaj Amrutur, Mohan Kumar, Anjana G.R, Alok Rawat and Sheetal Kumar |
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| A1.3 RELSPEC: A Framework for Early Reliability Refinement of Embedded Applications Saurav Kumar Ghosh, Aritra Hazra and Soumyajit Dey, IIT Kharagpur |
B1.3 On the Analysis of Reversible Booth’s Multiplier Sajib Mitra, Ahsan Chowdhury and Jakia Sultana |
C1.3 Ultra-fast cap-less LDO for dual lane USB in 28FDSOI Saurabh Singh and Gautam Kanungo, ST |
E1.2: Invited Talk: IBM - BlueMix Amit Mangalvedkar, IBM |
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| Session 2, Day 1 (January 5, 2015) 4.00 PM to 5.30 PM | ||||
Track A ROYAL BALLROOM |
Track B JAMAVAR(GROUND FLOOR) |
Track C KAMAL |
Track D GRAND BALLROOM |
Track E DIYA |
| Session A2: Embedded Systems Chair: Gautam Doshi, Intel |
Session B2: Design Implementation Chair: Amit Jain, Mediatek |
Session C2: Analog Chair: Vasantha Erraguntla, Intel |
Session D2: Special Session | Session E2: User Design Chair: Prasun Raha, Tabula |
| A2.1 Thermal Extension of the Total Bandwidth Server Ayoosh Bansal, Rehan Ahmed, Bhuvana Kakunoori, Parameswaran Ramanathan and Kewal Saluja, University of Wisconsin-Madison |
B2.1 Invited Talk: Better-than-Worst-Case Timing Design Adit Singh, Auburn University, USA |
C2.1 Invited Talk: RF/Analog design challenges in Advanced Technology Nodes Madhukar Reddy, V.P. Central Engineering, Maxlinear Inc., USA |
D2.1 : Invited Talk: Circuit and Architectural Innovations using Steep Switching Tunnel FETs Vijaykrishnan Narayanan, Penn State, USA |
E2.1: High Performance Computing using Cell-phone chipset Amit Bhatt and Shoeb Chikte, Dhirubhai Ambani Institute of ICT |
| A2.2 Thermal-Aware Test Data Compression Using Dictionary Based Coding Rajit Karmakar and Santanu Chattopadhyay, IIT-Kharagpur |
B2.2 Two Phase Write Scheme to Improve Low Voltage Write-Ability in Medium-Density SRAMs M Sultan M Siddiqui, Shailendra Sharad, Yogendra Sharma and Amit Khanuja, Synopsys |
C2.2 Any Capacitor Stable LVR Using Sub-Unity Gain Positive Feedback Loop in 65nm CMOS Saurabh singh and Nitin Bansal |
E2.2: Architecture and Design Automation of High Performance Arithmetic Architectures on FPGAs Ayan Palchaudhuri and Rajat Chakraborty, IIT-Kharagpur |
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| A2.3 CERI: Cost-Effective Routing Implementation Technique For Network-on-Chip Rimpy Bishnoi, Vijay Laxmi & Manoj Singh Gaur - NMIT, Jaipur, Radi Husin Bin Ramlee and Mark Zwolinski - University of Southampton |
B2.3 A CMOS 90nm Supply Noise Tolerant High Density 8T –NAND ROM Vinay Kumar, Ashish Kumar and Dhori Kedar Janardan, ST |
C2.3 A Wide Dynamic-Range Low-Power Signal Conditioning Circuit for Low-Side Current Sensing Application Rahul T., Bibhudatta Sahoo, Arya Sasidharakurup, Parvathy S. J. and Veeresh Babu Vulligaddala, Amrite University & ams Semiconductor |
D2.2: Invited Talk : The Spin on Spintronics Kaushik Roy and Anand Raghunathan, Purdue University, USA |
E2.3: Architectures for Embedded Vision Application using FPGA-based Platform Jai Gopal Pandey, Abhijit Karmakar, Chandra Shekhar and S. Gurunarayanan |
| A2.4 Way Halted Prediction Cache: An Energy Efficient Cache Architecture for Embedded Processors Neethu Mallya, Geeta Patil and Biju Raveendran |
B2.4 2SAT based Infeasibility Resolution during Design Rule Correction on Layouts with Multiple Grids Sambuddha Bhattacharya , Nitin Salodkar, Subramanian Rajagopalan, and Shabbir Batterywala |
C2.4 A wide tuning range LC quadrature phase oscillator employing mode switching Sivaramakrishna Rudrapati, Sharayu Jagtap and Shalabh Gupta, IIT-Bombay |
E2.4: A Pipelined Parallel Video Acquisition for Embedded Vision System on an XMOS Multicore Microcontroller Sudha Natarajan, Yuvaraj Velumani, Padma Lakshmi S and Srinivas Phani Chandra E, XMOS |
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| Session 3, Day 2 (January 6, 2015), 12.00 PM to 1.00 PM | ||||
Track A ROYAL BALLROOM |
Track B JAMAVAR(GROUND FLOOR) |
Track C KAMAL |
Track D GRAND BALLROOM |
Track E DIYA |
Session A3: Special Session Chair: Aloknath De, Samsung |
Session B3: Design Verification Chair: Narayana Pidugu, Xilinx |
Session C3: Devices & Circuits Chair: Dr. Devesh Dwivedi , IBM |
Session D3: Panel Discussion | Session E3: User Design Chair: Vivek Sabnis, AMD |
A3.1 Invited Talk: IoT Protocol Wars & the Way Forward |
B3.1 Formal Methods for Pattern Based Reliability Analysis in Embedded Systems Sumana Ghosh and Pallab Dasgupta, IIT Kharagpur |
C3.1 Block-level Electro-Migration Analysis(BEMA)for safer product life Radhika Gupta, ST , Rakesh Shenoy Panemangalore, Synopsys and Atul Bhargava, ST |
D3.1: Global Technology Progress in VLSI and Embedded Systems INDIA - Dr. V Kamakoti RUSSIA - Sergey Gavrilov BRAZIL - Leticia Maria Bolzani Poehls CHINA - Li, Xiaowei |
E3.1: Invited Talk:Sensors & Systems for IoT - next wave of opportunity Prasanth Perugupalli, MD, IMEC Ind E3.1: Keynote Talk (Cont…) |
A3.2 Invited Talk: Standards for an IoT Era |
B3.2 On Event Driven Modeling of Continuous Time Systems Dushyant Juneja, Analog Devices |
C3.2 Recessed MOSFET in 28 nm FDSOI for better breakdown characteristics Kranthi Nagothu, RadhaKrishnan Sithanandam and Rama S. Komaragiri, NIT Calicut & ST |
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C3.3 Design of high speed ternary full adder and three-input XOR circuits using CNTFETs |
E3.2: Enabling low power battery operated Wlan devices for IoT Saket Jalan, TI |
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| Session 4, Day 2 (January 6, 2015) 2.45 PM to 3.45 PM | ||||
Track A ROYAL BALLROOM |
Track B JAMAVAR(GROUND FLOOR) |
Track C KAMAL |
Track D GRAND BALLROOM |
Track E DIYA |
Session A4: IOT & Product Chair:Dheemanth Nagaraj, Intel |
Session B4: Design Implementation Chair: Rahul Rao, IBM |
Session C4: Devices & Circuits Chair: Sourav Saha, IBM |
Session D4: Test & Reliability Chair: Prashant Shrivastava, C2SiS |
Session E4: User Design Chair: K.A Rajagopal, TI |
A4.1 A Frequency Scan Scheme for PLL-Based Locking To High-Q MEMS Resonators |
B4.1 A Novel CKE-ODT-CSN Encoding Scheme in DDR Memory Interface Vinod Inipodu Murugan, Narayanan Mayandi and Sendhil Arul |
C4.1 A noise aware CML latch modelling for large system simulation Abhijit Chatterjee, Debesh Bhatta and Suvadeep Banerjee, Georgia Tech |
D4.1 New Methods for Simulation Speed-up and Test Qualification With Analog Fault Simulation Lakshmanan Balasubramanian, Devanathan VR and Rubin Parekhji, TI |
E4.1: Personalized smart network using wearable devices in an IOT configuration Sachin Kamat and Tushar Behera |
A4.2 NFC Products For Pervasive Healthcare |
B4.2 A Design Approach for Compressor Based Approximate Multipliers Naman Maheshwari, Zhixi Yang, Jie Han and Fabrizio Lombardi, BITS-Pilani & Univeristy of Alberta |
C4.2 An Efficient Transition Detector Exploiting Charge Sharing Yu Wang and Adit Singh |
D4.2 Efficient Peak Power Estimation using Probabilistic Cost-Benefit Analysis Prabhat Mishra, Hadi Hajimiri and Kamran Rahmani, University of Florida |
E4.2: Design Automation for Low Skew Global Clock Distribution - Shraddha padiyar, Shanamaz Ganuga and Animesh Jain |
| A4.3 Hardware Solution For Real-time Face Recognition Gopinath Mahale, Hamsika Mahale, Arnav Goel, S.K. Nandy, Sukumar Bhattacharya and Ranjani Narayan, IISc-Bangalore |
B4.3 Integrated 16-channel Transmit and Receive Beamforming ASIC for Ultrasound Imaging Chandrashekar Dusa, Samiyuktha Kalalii, Omkeshwar B and Rajalakshmi P, IITH |
C4.3 A High-Efficiency Switched-Capacitance HTFET Charge Pump For Low-Input-Voltage Applications |
D4.3 DFT Technique for Quick Characterization of Flash Offset in Pipeline ADCs Pradeep Nair and Nagarajan Viswanathan, TI |
E4.3: Parameterized and Re-usable Jitter Model for Serial and Parallel Interfaces Amlan Chakrabarti and Malathi Chikkanna, AMD |
| Session 5, Day 2 (January 6, 2015) 4.00 PM to 5.30 PM | ||||
Track A ROYAL BALLROOM |
Track B JAMAVAR(GROUND FLOOR) |
Track C KAMAL |
Track D GRAND BALLROOM |
Track E DIYA |
| Session A5: Product & Emerging Technologies Chair: Jai Balakrishnan, TI |
Session B5: Design Implementation Chair: Srikanth Raghavan, ARM |
Session C5: Special Session on Sensors Chair: Jagannanthan Venkataraman, TI |
Session D5: Test & Reliability Chair: Sandeep Pendharkar, AMD |
Session E5: User Design Chair: Anurag Gupta, LGE |
A5.1: Invited Talk:India Microprocessor |
B5.1 Thermal-aware application scheduling on device-heterogeneous embedded architectures Karthik Swaminathan, Jagadish Kotra, Huichu Liu, Jack Sampson, Mahmut Kandemir and Vijaykrishnan Narayanan |
C5.1: Invited Session 1: Sensors to Systems to Applications Ramgopal Rao, IIT Mumbai |
D5.1 Invited Talk: Recent Advances in Test Compression Nilanjan Mukherjee, Engineering Director, Test Synthesis, Silicon Test Solution, Mentor Graphics Corp., USA |
E5.1: Test pattern volume reduction using RRFA based Test Point Insertion Vineet Srivastava, Vijay Premchandar and Satish Ravichandran, PMC-Sierra |
| B5.2 Exploring Scope of Power Reduction with Constrained Physical Synthesis Kaustav Guha-Cadence, Sourav Saha and Ricardo Nigaglioni, IBM |
D5.2 Framework for Selective Flip-Flop Replacement for Soft-Error Mitigation Pavan Vithal Torvi, Devanathan VR and Kamakoti V, IIT-M |
E5.2: Performing SoC level SDF Simulations using Testbench Acceleration |
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| A5.3 Robot navigation using neuro-electronic hybrid systems Jude Baby, Grace Mathew Abraham, Bharadwaj Amrutur and Sujit Kumar Sikdar, IISc |
B5.3 All Optical Implementation of Mach-Zehnder Interferometer based Reversible Sequential Counters Pratik Dutta, Chandan Bandyopadhyay and Hafizur Rahaman |
C5.2: Invited Session 2: Development of MEMS sensors for agriculture |
D5.3 Diagnostic Tests for Pre-Bond TSV Defects Bei Zhang and Vishwani Agrawal, Auburn University |
E5.3: A novel approach to detect manufacturing faults in functional clock paths using ATPG Rajesh Mittal, TI |
| A5.4 Comparison of Off-chip Training Methods for Neuromemristive Systems Cory Merkel and Dhireesha Kudithipudi, RIT USA |
B5.4 Design of a Compact Reversible Carry Look-Ahead Adder Using Dynamic Programming Nusrat Jahan Lisa and Hafiz Md Hasan Babu, University of Dhaka |
D5.4 Few Good Frequencies for Power-Constrained Test Sindhu Gunasekar and Vishwani Agrawal |
E5.4: System State Retention Verification using ATPG tool for Debug Prakash Venkitaraman and Jais Abraham, AMD |
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| Session 6, Day 3 (January 7, 2014): 12.00 PM to 1.00 PM | ||||
Track A ROYAL BALLROOM |
Track B JAMAVAR(GROUND FLOOR) |
Track C KAMAL |
Track D GRAND BALLROOM |
Track E DIYA |
| Session A6: System Level Design Chair: Shankar Ramakrishnan, TI |
Session B6: Poster Session | Session C6: Digital & FPGA Chair: Manish Saluja, Samsung |
Session D6:Test & Reliability Chair: Triveni Rachapalli, Qualcomm |
Session E6: User Design Chair: Ravindra Babu, Cypress |
A6.1 OcNoC: Efficient One-cycle Implementation of Routers for 3D Mesh Networks on Chip |
Poster Session 1 | C6.1 Power Optimization Techniques for DDR3 SDRAM Preeti Ranjan Panda, Vishal Patel, Praxal Shah, Namita Sharma - IIT-Delhi, Vaidyanathan Srinivasan and Dipankar Sarma - IBM |
D6.1 Invited Talk: Volume Diagnosis for Yield Improvement Wu-Tung Cheng, Mentor Graphics Corp., USA and Sudhakar M. Reddy, University of Iowa, USA |
E6.1: A Paradigm Shift to SoC Verification - Scalable Methods to Bridge the Gap between IP and SoC Verification Gaurav Gupta, Tejbal Prasad, Rohit Goyal and Sachin Jain, Freescale |
A6.2 Mode-Division-Multiplexed Photonic Router for High Performance Network-on-Chip |
C6.2 A Novel Ternary Content-Addressable Memory (TCAM) Design Using Reversible Logic Dinesh Kumar Selvakumaran and Noor Mahammad Sk |
D6.2 Using Boolean Tests to Improve Detection of Transistor Stuck-open Faults in CMOS Digital Logic Circuits Xijiang lin, Sudhakar Reddy and Janusz Rajski |
E6.2: OVM test-bench reuse from simulation to emulation |
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| A6.3 A Hardware and Thermal Analysis of DVFS in a Multi-Core System with Hybrid WiNoC Architecture Sri Harsha Gade, Hemanta Kumar Mondal and Sujay Deb |
C6.3 Design and Analysis of Delay Elements for 2-Phase Bundled-Data Asynchronous Circuits |
D6.3 On-Chip Current Sensors and Neighbourhood Comparison Logic to Detect Resistive-Open Defects in SRAMs Felipe Lavratti, Leticia Maria Bolzani Poehls, Fabian Luis Vargas, Andrea Calimera and Enrico Macii |
E6.3: Strategies for Verifying Liveness Problems using Formal Verification Srobona Mitra, Pradeep Nalla, Udo Krautz and Viresh Paruthi, IBM |
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| Session 7, Day 3 (January 7, 2015) 2.45 PM to 3.45 PM | ||||
Track A ROYAL BALLROOM |
Track B JAMAVAR(GROUND FLOOR) |
Track C KAMAL |
Track D GRAND BALLROOM |
Track E DIYA |
| Session A7:System Level Design Chair: Shankar Ramakrishnan, TI |
Session B7: Poster Session | Session C7: Digital & FPGA Chair: Manish Saluja, Samsung |
Session D7: EDA Chair: Arvind N V, Cadence |
Session E7: User Design Chair: Pradeep Salla, Mentor Graphics |
A7.1 Bandwidth Adaptive Nanophotonic Crossbars with Clockwise/Counter-Clockwise Optical Routing |
Poster Session 2 | D7.1 Statistical Analysis of 64Mb SRAM for Optimizing Yield and Write Performance Gaurav Narang, Pragya Sharma, Mansi Jain and Anuj Grover, ST |
E7.1: Efficient packet generation and interfacing with Verilog/SV testbench for logic verification of networking devices Vikalp Khandelwal and Rishikesan Parthiban, C2Si |
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A7.2 Effects of Nondeterminism in Hardware and Software Simulation with Thread Mapping |
D7.2 Recursive Wirelength Model for Analytical Placement BNB RAY and Shankar Balachandran, IIT-M |
E7.2: Unique generic solution for all verification needs |
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C7.3 SPAA-Aware 2D Gaussian Smoothing Filter Design Using Efficient Approximation Techniques |
D7.3 A Nonlinear Analytical Optimization Method for Standard Cell Placement of VLSI Circuits Sameer Pawanekar, Kalpesh Kapoor and Gaurav Trivedi |
E7.3: High-Level SoC modeling framework for Latency and throughput estimation Sharan Basappa & Abhishek Ghate, HCL |
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| Session 8, Day 3 (January 7, 2015) 4.00 PM to 5.30 PM | ||||
Track A ROYAL BALLROOM |
Track B JAMAVAR(GROUND FLOOR) |
Track C KAMAL |
Track D GRAND BALLROOM |
Track E DIYA |
| Session A8: HPC Chair: Prof. Madhu Mutyam,IIT-M |
Session B8: LOC | Session C8: Digital & FPGA Chair: Sid Sinari, Broadcom |
Session D8: EDA Chair: Arpan Sircar, Mentor Graphics |
Session E8: User Design |
A8.1 Can you trust your memory trace?: A comparison of memory traces from binary instrumentation and simulation |
B8.1 Special Session : Continuous-Flow Biochips: Current platforms and emerging research challenges Paul Pop, Technical University of Denmark (DTU), Denmark |
C8.1 An FPGA-based Architecture for Local Similarity Measure for Image/Video Processing Applications Jai Gopal Pandey, Abhijit Karmakar, Chandra Shekhar and S. Gurunarayanan, CSIR |
D8.1 Monitoring AMS Simulation: From Assertions to Features Antara Ain and Pallab Dasgupta, IIT Kharagpur |
E8.1: Simplified power switch design methodology for big memory macros Kedar Rajpathak, AMD |
A8.2 Exploration of Migration and Replacement Policies for Dynamic NUCA over Tiled CMPs |
C8.2 FPGA based Scalable Fixed Point QRD core using Dynamic Partial Reconfiguration Gayathri R Prabhu, Bibin Johnson and Dr. J Sheeba Rani | D8.2 BDD-based Synthesis for All-optical Mach-Zehnder Interferometer Circuits Eleonora Schonborn, Kamalika Datta, Robert Wille, Indranil Sengupta, Hafizur Rahaman and Rolf Drechsler |
E8.2: Know Thy Ropes - For Accelerated Timing Constraint Analysis, Refinement And Validation |
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| A8.3 Cross-Layer Exploration of Heterogeneous Multicore Processor Configurations Santanu Sarma and Nikil Dutt, UC Irvine |
C8.3 A High-performance Energy-efficient Hybrid Redundant MAC for Error-resilient Applications |
D8.3 Optimized Logarithmic Barrel Shifter in Reversible Logic Synthesis Sajib Mitra and Ahsan Chowdhury |
E8.3: Qualifier Metric Based Critical Region Marking towards Targeted Design Optimization Sourav Saha, Sridhar Rangarajan, George Antony and Vinay Singh, IBM |
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| A8.4 Micro-architectural Enhancements in Distributed Memory CGRAs for LU and QR Factorizations Farhad Merchant, Arka Maity, Mahesh Mahadurkar, Kapil Vatwani, Ishan Munje, Madhava Krishna, Nalesh S, Nandhini Gopalan, Soumyendu Raha, S K Nandy and Ranjani Narayan, IISc-Bangalore |
C8.4 Energy Aware Computation Driven Approximate DCT Architecture for Image Processing Vikas Kaushal, Ankur Jaiswal, Bharat Garg and G. K. Sharma, IIITM, Gwalior |
E8.4: Framework of an optimal design partition process for a multi-level hierarchical VLSI design Chandrika M, Charudhattan Nagarajan, Rajashree Srinidhi, sabarikumar chinnakonda, Satheesh Kumar Sompalle and Allmin Ansari, IBM |
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