Plenary Talks

Achieving Energy Efficiency by HW/SW Co-design

Shekher Borkar, Intel

Abstract: Compute performance increased by orders of magnitude in the last few decades, made possible by continued technology scaling, increasing frequency, providing integration capacity to realize novel architectures, and reducing energy to keep power dissipation within limit. The technology treadmill will continue, and one would expect to reach Exascale level performance this decade; however, it’s the same Physics that helped you in the past will now pose some barriers—Business as usual will not be an option. The energy and power will pose as a major challenge. Memory & communication bandwidth with conventional technology would be prohibitive. Orders of magnitude increased parallelism, let alone extreme parallelism due to energy saving techniques, would increase unreliability. And programming system will be posed with even severe challenge of harnessing the performance with concurrency. We will discuss potential solutions in all disciplines, such as circuit design, system architecture, system software, programming system, and resiliency—in the true spirit of hardware-software- technology co-design—where all levels in the system stack are harmonized to deliver the most energy efficient system.

2. Shekhar Borkar
3. Intel

Bio: Shekhar Borkar received M.Sc in Physics from University of Bombay in 1979, MSEE from University of Notre Dame in 1981 and joined Intel Corp, where he worked on the 8051 family of microcontrollers, and Intel’s supercomputers. Shekhar is an Intel Fellow, an IEEE Fellow, and Director of Extreme-scale Technologies.

From Embedded Systems to Systems of Systems

Herman Kopetz, Vienna University of Technology, Austria

Abstract: Most of today’s machines, e.g., automotive engines, production machinery or even consumer devices, such as a washing machine, are controlled by an embedded computer system. It is assumed that the widespread integration of these existing embedded computer systems and data bases into systems-of-systems will provide new synergistic services, make better use of the available information, lead to new insights, improve current economic processes and thus create greater wealth. Fueled by the dramatic technological progress in the area of wire-bound and wire-less communication, this integration is already happening on a wide scale in industry. From the viewpoint of computer science, the domain of Systems-of-Systems (SoS) is a relatively new field that poses significant new research challenges. The table below characterizes a system of system by listing some distinguishing properties of a SoS compared to those of a monolithic system. If we look at this table we see that the listed characteristics of a SoS violate many of the fundamental assumptions that are taken for granted in the established monolithic system design process. For example, there is no central development authority, fixed specification, coordinated evolution, or final acceptance test of a SoS. In our view, the most differentiating characteristics of a SoS compared to a monolithic system are the autonomy of the constituent systems (CS) and their means to represent information, emergent phenomena at the SoS level and uncoordinated evolution of the CSs. From the perspective of a SoS the CSs that form an SoS are independent, tightly integrated in their local environments and must be continually adapted to remain relevant to their ever-changing local environments. On October 1, 2013 the new European FP7 research project AMADEOS (Architecture for Multi-criticality Agile Dependable Evolutionary Open System-of- Systems) has started with the following objectives: It is the objective of this research proposal to bring time awareness and evolution into the design of System-of-Systems (SoS), to establish a sound conceptual model, a generic architectural framework and a design methodology, supported by some prototype tools, for the modeling, development and evolution of time-sensitive SoSs with possible emergent behaviors. The proposed open and agile architecture will focus on mixed-criticality Cyber- Physical Systems (CPS) with guaranteed responsiveness. This presentation will focus on the research issues that are posed by the integration of embedded systems into systems of systems and will present the research approach taken in the AMADEOS project. The project is supported by the European Commission under grant agreement 610535.

2. Hermann Kopetz
3. Vienna University of Technology, Austria

Bio: Hermann Kopetz received his PhD degree in physics "sub auspiciis praesidentis" from the University of Vienna, Austria in 1968. He was a manager of a computer process control department at Voest Alpine in Linz, Austria, before accepting an appointment as a Professor for Computer Process Control at the Technical University of West-Berlin. Since 1982 he has been professor for Real-Time Systems at the Vienna University of Technology, Austria. From 1990 to 1992 Kopetz was chairman of the IEEE Technical Committee on Fault- Tolerant Computing and was elected to the grade of a “Fellow of the IEEE” in 1993. Dr. Kopetz was the Chairman of the IFIP WG 10.4 on Dependable Computing and Fault-Tolerance from 1996 to 1998. In 1998 he was elected to become a full member of the Austrian Academy of Science. Dr. Kopetz has been a Visiting Professor at the University of California at Irvine in 1993 and at St. Barbara in 1996. Dr. Kopetz is one of the founders of the spin-off company TTTech, established in 1998. From July 2000 to July 2005 Dr. Kopetz served as an advisor for the Austrian Government on Science Policy. Dr. Kopetz received the IEEE Computer Society 2003 Technical Achievement Award with the citation: For outstanding contributions to the field of safety-critical real-time computing. In 2007 Dr. Kopetz received the "Docteur honoris causa" from the Universitè Paul Sabatier, Toulouse. In December 2007 Dr. Kopetz was awarded the technical achievement award of the IEEE TC on Real-Time Systems. For the period 2007 - 2009 Dr. Kopetz is member of the IST Advisory Group, the Advisory Group for the ICT theme in FP7. Furthermore, he serves as chairman for the Scientific Board of the Embedded Systems Institute (Eindhoven, NL) and for the Scientific Board of ARC (Seibersdorf, A). Dr Kopetz has published a widely used textbook on Real-Time Systems and more than 150 papers on the topic of dependable embedded systems. He holds more than thirty patents. research interests focus at the intersection of real-time systems, fault-tolerant systems, and distributed systems. He is the chief architect of the Time-Triggered Protocol (TTP) for distributed fault-tolerant real-time systems, which evolved out of the MARS project at the Technical University of Vienna. In the last few years, Dr. Kopetz and his research group work in the field of automotive and aerospace electronics. He is presently involved in two large EC funded research projects, namely the FP6 Integrated Project DECOS and the FP6 Network of Excellence ARTIST2 Dr. Kopetz.

Future of Nano CMOS Technology

Hiroshi Iwai, Tokyo Institute of Technology, Japan

Abstract: Although silicon-based CMOS devices have dominated the integrated circuit applications over the past few decades, it is expected that the development of CMOS would reach its limits after the next decade because of the difficulties in downsizing and some fundamental limits of MOSFETs. However, there are no promising candidates which can replace CMOS with better performance with high-density integration for the moment. Thus, we have to stick to the CMOS devices until its end. In order to pursue the downsizing of CMOS for another decade, the development of new technologies is becoming extremely important. Not all the companies can necessarily develop the most advanced technology timely and the competition between the leading semiconductor manufacturing companies becomes very severe for their survive. The current status of the frontend of the technology is as follows: New device structures (FinFET, Tri-gate, and Si-nanowire MOSFETs) are replacing conventional planar MOSFETs. Continuous innovation of High-k/metal gate technologies has enabled EOT scaling down to 0.9 – 0.7 nm in production, however, new materials are necessary for further EOT scaling. Recent advances in new channel material such as III-V/Ge shows promising device performances, however, it is still behind of the state of the art Si-CMOS technologies. comparable to state of the art Si-based MOSFETs. Device demonstration on emerging technologies (such as Tunnel FET, Junctionless FET, Carbon-based FET..) is increasing, But we cannot draw a successful story to replace the Si-CMOS and much longer time is needed for implementation of these technologies in future generation devices.

2. Hiroshi Iwai
3. Tokyo Institute of Technology, Japan

Bio: Hiroshi Iwai received the B.E. and Ph.D. degrees in electrical engineering from the University of Tokyo and worked in the research and development of integrated circuit technology for more than 25 years in Toshiba. He is now a professor of Frontier Research Center and Dept. of Electronics and Applied Physics, Interdisciplinary Graduate School of Science and Engineering, Tokyo Institute of Technology, Yokohama, Japan. Since joining Toshiba, he has developed several generations of high density static RAM's, dynamic RAM's and logic LSI's including CMOS, bipolar, and Bi-CMOS devices. He has also been engaged in research on device physics, process technologies, and T-CAD related to small-geometry MOSFETs and high speed bipolar transistors. He has authored and coauthored more than 1,000 international and 400 domestic journal/conference papers. His current research interests are Nano CMOS, Power and Photovoltaic Devices: Si Nanowire and III-V MOSFETs, GaN & Diamond Power devices, Si-nanowire & silicide photovoltaic devices, and High-k gate insulator & Metal/silicide S/D technologies. Dr. Iwai is, a fellow of IEEE, a fellow of Institute of Electrical Engineers Japan, a fellow of the Japan Society Applied Physics, and a fellow of the Institute of Electronics, Information and Communication Engineers of Japan. He is a recipient of many prize and awards such as J.J. Ebers Award, Prizes for Science and Technology by the Minister of Japan.

Testing and Debugging VLSI System

Masahiro Fujita, Tokyo University

Abstract: When testing circuits, advanced semiconductor technology needs wider ranges of attention, i.e., not just stuck-at faults but many others. From the viewpoint of logical functionality, functional faults are most general and can cover varieties of faults actually happening in the modern VLSI systems. As there are so many possible ways of faults in functional faults, their complete testing has been believed to be out of practice. Thanks to the recent advances in tools for Boolean reasoning, complete testing of such functional faults can be very practical, if we use implicit methods instead of traditional explicit methods. The researches have shown that very small numbers of test vectors can actually guarantee complete checking of all possible fictional faults. Moreover, functional faults can also represent logical bugs, if the bugs are within the target faulty region. In this talk, we review the state-of-the-art techniques for testing, verifying, and diagnosing VLSI designs and implementations with emphasizing future perspective.

2. Masahiro Fujita
3. Tokyo University

Bio: Masahiro Fujita received his Ph.D. in Information Engineering from the University of Tokyo in 1985 on his work on model checking of hardware designs by using logic programming languages. In 1985, he joined Fujitsu as a researcher and started to work on hardware automatic synthesis as well as formal verification methods and tools, including enhancements of BDD/SAT-based techniques. From 1993 to 2000, he was director at Fujitsu Laboratories of America and headed a hardware formal verification group developing a formal verifier for real-life designs having more than several million gates. The developed tool has been used in production internally at Fujitsu and externally as well. Since March 2000, he has been a professor at VLSI Design and Education Center of the University of Tokyo. He has done innovative work in the areas of hardware verification, synthesis, testing, and software verification-mostly targeting embedded software and web-based programs. He has been involved in a Japanese governmental research project for dependable system designs and has developed a formal verifier for C programs that could be used for both hardware and embedded software designs. The tool is now under evaluation jointly with industry under governmental support. He has authored and co-authored 10 books, and has more than 250 publications. He has been involved as program and steering committee member in many prestigious conferences on CAD, VLSI designs, software engineering, and more. His current research interests include synthesis and verification in SoC (System on Chip), hardware/software co-designs targeting embedded systems, digital/analog co- designs, and formal analysis, verification, and synthesis of web-based programs and embedded programs.

Brighter side of Dark Silicon

S K Nandy, IISc Bangalore

Abstract: Desktop supercomputing is a felt need for a large class of challenging and compelling applications spanning healthcare to climate modeling. In keeping with Moore's Law, as technology nodes continue to shrink, we enter the era of "Dark Silicon", where we are confronted with the Utilization Wall. General purpose processing on multi-cores is no more a panacea for the ILP, Memory, and Power wall. In this presentation, we will seek answers to the question: Can (post silicon) runtime reconfiguration of hardware to compose custom datapaths and processing cores on demand serve as the brighter side of dark silicon for desktop supercomputing?

2. S K Nandy
3. IISc Bangalore

Bio: S. K. Nandy is a Professor at the Supercomputer Education and Research Centre, and the Department of Electronic Systems Engineering of the Indian Institute of Science, Bangalore, India. He is the convener of the Computer Aided Design Laboratory, a state-of-the-art laboratory for VLSI Systems Design set up in 1985 with the assistance of the UNDP and the Department of Electronics, Government of India. His current research interests include Dataflow and Flexible Multi-core Processor Architectures, Micro-architectural and Compiler optimizations for power and performance, Chip Multiprocessors (CMPs) and Runtime Reconfigurable Multiprocessor Systems on Chips (MP-SoCs), and Cloud Systems. Prof. Nandy has over 130 research publications in International Journals and Proceedings of International Conferences that highlight his research contributions. He is responsible for setting up Morphing Machines (url: www.morphingmachins.com), a technology incubated start-up company from the Indian Institute of Science, engaged in the development of Reconfigurable Silicon Cores, where he holds the position of Honorary Chief Scientist. Prof. Nandy obtained his B.Sc.(Hons.) degree in Physics from the Indian Institute of Technology, Kharagpur in 1977. He obtained his B.E.(Hons.) degree in Electrical Communications Engineering in 1980, M.Sc.(Engg.) degree in Computer Science and Engineering in 1987, and Ph.D degree in Computer Science and Engineering in 1989 from the Indian Institute of Science, Bangalore.

Net of Things to Internet of Things

Wei Zhao,Macau Univ.

Abstract: Internet of Things (IoT) is a networking infrastructure for cyber-physical systems. With IoT, physical objects should be seamlessly integrated into an Internet- like system so that the physical objects and cyber-agents can interact each other in order to achieve mission-critical objectives. Internet of Things (IoT) should have tremendous application potential and hence has become popular in recent years, attracting great attentions from both academic research and industrial development. In this talk, we will first focus on fundamental issues related to IoT. We aruge most of R/D work has focused on "Net of Things". Efforts are needed to create "Internet of Things". We address principles that should guide research and development of IoT. We will then present several approaches that may lead to implementation of IoT and analyze their advantages and disadvantages. Finally, we will discuss critical issues that must be addressed in order to fully realize the objectives and potentials of IoT.

2. Wei Zhao
3. Macau Univ.

Bio: Wei Zhao is currently the Rector of the University of Macau (UM). Before joining the University of Macau, Professor Zhao served as the Dean of the School of Science at Rensselaer Polytechnic Institute, Director for the Division of Computer and Network Systems in the U.S. National Science Foundation, and Senior Associate Vice President for Research at Texas A&M; University. As an IEEE Fellow, Professor Zhao has made significant contributions in distributed computing, real-time systems, computer networks, and cyberspace security. His research group has been well recognized and received numerous awards and prizes including the outstanding paper award (1992) from the IEEE International Conference on Distributed Computing Systems, the best paper award (1998) from the IEEE National Aerospace and Electronics Conference, an award on technology transfer from the Defense Advanced Research Program Agency in 2002, and the best paper award (2008) from the IEEE International Communication Conference. In 2007, he received the IEEE Transactions on Parallel and Distributed Systems Outstanding Achievement Award. Professor Zhao is the holder of two U.S. patents and has published over 300 papers in journals, conferences, and book chapters. In 2011, he was named by the Ministry of Science and Technology as the Chief Scientist of the national 973 Internet of Things Project on cyber-physical networking systems. Recognizing his accomplishments in education leadership and scientific research, Wei Zhao has been a recipient of 12 Honoral doctoral degrees.

Your Synthesis is Broken @ 14nm: Physical to the Rescue

Sanjiv Taneja,Cadence

Abstract: The small world of sub-20nm is already upon us and has brought a new set of challenges for RTL designers as the race for best PPA (performance, power, and area) continues unabated. Challenges include giga-scale integration of new functionality, new physics effects, new device structures such as FinFETs, interconnect stacks with vastly varying resistance characteristics from bottom to top layers in a non-linear fashion and process variation. These challenges are raising several questions. Can RTL synthesis handle giga-scale, giga-hertz designs in a timeframe of market relevance? Can logic synthesis perform accurate and predictive modeling of the interconnect stack, vias and other physical effects in RTL? How do new device structures affect dynamic and leakage power tradeoff and library choices? How do logic structuring, cell selection, clock gating, and DFT choices change to anticipate and handle routing congestion? And how do we ensure strong correlation between logic synthesis and P&R;/signoff? This talk will explore these challenges and provide an overview of state-of-the-art technology to address them in a predictive and convergent design flow.

2. Sanjiv Taneja
3. Cadence

Bio: Sanjiv Taneja is VP of Product Engineering for the Front End Design Group at Cadence Design Systems. Prior to assuming this role in 2010, he led Cadence's Encounter Test R&D; group for over five years. He joined Cadence from Bell Laboratories where he led the development of transistor-sizing based technology for low power design. Sanjiv holds a BS degree in EE from IIT New Delhi, MS in Computer Science from Ohio State University and MBA from NYU.

Combining Advanced Fault Models and Efficient Test Methods

Janusz Rajski,Mentor Graphics

Abstract:Semiconductor manufacturing always had to balance the desired product quality with the impact on the design process (silicon area, design time) and the cost of manufacturing test. Fault models are used to achieve the quality objectives. At 130 nm the industry started using the transition fault model in addition to the stuck-at fault. Since then we have added multiple detection capabilities, timing information, layout, and transistor-level models of standard cell libraries. In 2001 test compression was introduced, on top of scan, to reduce the cost of manufacturing test. What other technologies will be needed to address the issue of growing design sizes, increasing volume of test data, and longer test times? Will those be new breakthroughs in test compression, logic BIST or hybrids?

2. Janusz Rajski
3. Mentor Graphics

Bio: Janusz Rajski received the M.S. degree in electrical engineering from the Technical Uni-versity of Gdansk, Gdansk, Poland, in 1973, and the Ph.D. degree in electrical engineering from the Poznan University of Technology, Poznan, Poland. He is a chief scientist and the director of engineer-ing for the Silicon Test Solutions products group at Mentor Graphics. He has published more than 200 research papers in these areas and is co-inventor of 80 US patents. He is also the principal inventor of Embedded Deterministic Test (EDT(tm)) technology used in the first commercial test compression prod-uct TestKompress(R). He was co-recipient of the 1993 Best Paper Award for the paper on logic synthesis published in the IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, co-recipient of the 1995 and 1998 Best Paper Awards at the IEEE VLSI Test Symposium, co-recipient of the 1999 and 2003 Honorable Mention Awards and the 2012 Most Significant Paper Award at the IEEE International Test Conference, co-recipient of the 2010 Best Paper Award at the IEEE European Test Symposium, co-recipient of the 2008 Best Paper Award at the Asian Test Symposium, and 2009 Best Paper Award at the VLSI Design, as well as co-recipient of the 2006 IEEE Circuits and Systems Society Donald O. Pederson Outstanding Paper Award recognizing the paper on embedded deterministic test published in the IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. He served as Program Chair of the IEEE International Test Conference. In 2009 he received the Stephen Swerling Innovation Award from Mentor Graphics "for his breakthrough innovation, TestKompress, and his many contributions to revitalizing Mentor's DFT business to its current position as #1 test business in EDA"". In 2011 Janusz was elevated to the grade of IEEE Fellow for "contributions to VLSI circuit testing and test compression". In 2013 he was awarded an honorary doctorate from the Poznan University of Technology, Poznan, Poland.

Design and Test Challenges for Cyber-Physical Systems

Prof. Zebo Peng,Linköping Univ.

Abstract: There is an exponentially increasing number of cyber-physical systems where the computational components interact with the physical world in a tightly manner. Many of these systems are nowadays used for safety-critical applications, such as automotive electronics and medical equipment, with stringent reliability and real-time requirements. At the same time, with silicon technology scaling, integrated circuits used to implement the computational components of these systems are built with smaller transistors, operate at higher clock frequency, run at lower voltage levels, and operate very often at higher temperature. Consequently, they are subject to more faults and interferences. We are therefore facing the challenge of how to build reliable and predictable cyber-physical systems with unreliable and unpredictable components. This talk will discuss the design of cyber-physical systems for safety-critical applications by considering both fault-tolerance and real-time predictability at the same time. It will describe several key challenges and some emerging solutions to the design and test of such systems. In particular, it will present time-redundancy based fault-tolerance techniques to address transient faults which have become more and more common in nano-scale technology. It will also present several technology trends and research directions in the field of cyber-physical systems.

2. Prof. Zebo Peng
3. Linköping Univ.

Bio: Zebo Peng received his Ph.D. in Computer Science from Linköping University in 1987. He has been Professor and Director of the Embedded Systems Laboratory at Linköping University since 1996, and served as the head of the Swedish National Graduate School in Computer Science in 2006-2008. His current research interests include design and test of embedded systems, electronic design automation, SoC testing, fault tolerant design, hardware/software co-design, and real-time systems. He has published over 350 technical papers and four books in these areas, and has received four best paper awards and a best presentation award in major international conferences. He serves currently as Associate Editor of the IEEE Transactions on VLSI Systems, the VLSI Design Journal, and the EURASIP Journal on Embedded Systems. He has served on the program committee of a dozen international conferences, including ATS, DATE, DDECS, DFT, ETS, IOLTS, RTCSA, and VLSI-SOC, and was the Program Chair of DDECS’04, ETS’07, DATE'08, and ETS’13.

Carbon Nanotube Computer: Transforming Scientific Discoveries into Working Systems

Subhasish Mitra,Stanford Univ.

Abstract: Carbon Nanotube Field Effect Transistors (CNFETs) are excellent candidates for building highly energy-efficient future electronic systems. Unfortunately, carbon nanotubes are subject to substantial inherent imperfections that pose major obstacles to large-scale CNFET digital systems. A combination of design and processing techniques overcomes these challenges by creating robust CNFET digital circuits that are immune to these inherent imperfections. This imperfection-immune design paradigm enables the first experimental demonstration of the carbon nanotube computer, and, more generally, arbitrary CNFET digital systems. Monolithically-integrated three-dimensional CNFET circuits will also be discussed. This research was performed at Stanford University in collaboration with Prof. H.-S. Philip Wong and several graduate students.

2. Subhasish Mitra
3. Stanford Univ.

Bio: Professor Subhasish Mitra directs the Robust Systems Group in the Department of Electrical Engineering and the Department of Computer Science of Stanford University, where he is the Chambers Faculty Scholar of Engineering. Prior to joining Stanford, he was a Principal Engineer at Intel Corporation. He received Ph.D. in Electrical Engineering from Stanford University. Prof. Mitra's research interests include robust system design, VLSI design, CAD, validation and test, and emerging nanotechnologies. His X-Compact technique for test compression has been key to cost-effective manufacturing and high-quality testing of a vast majority of electronic systems, including numerous Intel products. X-Compact and its derivatives have been implemented in widely-used commercial Electronic Design Automation tools. The QED and IFRA techniques, created jointly with his students, have shown outstanding results in overcoming critical bottlenecks in post-silicon validation and debug for several commercial hardware platforms, and have been characterized as "breakthrough" in a Research Highlight in the Communications of the ACM (CACM). His work on carbon nanotube imperfection- immune digital VLSI, jointly with his students and collaborators, resulted in the demonstration of the first carbon nanotube computer, and it was featured on the cover of NATURE. The National Science Foundation (NSF) presented this work as a Research Highlight to the United States Congress, and it also was highlighted as "an important, scientific breakthrough" by the BBC, Economist, EE Times, IEEE Spectrum, MIT Technology Review, New York Times, Scientific American, Time, Wall Street Journal, Washington Post, and numerous other organizations worldwide.

Art and Science of Benchmarking Ultra Low Power Micro-controllers.

Mahesh Mehendale,Texas Instruments

Abstract: Ultra-low power micro-controllers (MCUs) are at the heart of the devices forming the “Swarm at the Edge of the Cloud”. With the Internet of Things (IoT) increasingly becoming a reality, many ultra-low power MCUs have been released in the market and the trend of further pushing the low power envelop is here to stay. Every ULP MCU announcement claims low power leadership – using a unique metric at operating conditions and system context for which it’s been optimized. The ULP metrics of interest vary depending on the application requirements and hence it’s important to take a holistic view to select the most power optimal MCU. In this talk, we discuss some of the commonly used low power metrics and their inter-relationships. We present architecture level, design level and process- technology level techniques to optimize these metrics and also highlight how looking at one metric (e.g. uA/MHz) in isolation can be misleading. We show that in IoT context, a combination of metrics needs to be considered, and how the choice of these metrics depends on the operating conditions and system context. We propose that a platform based approach and dynamically adaptive implementations are key to not only winning the air-wars (Art of benchmarking) but also the ground-wars (Science of benchmarking) of ultra-low power leadership.

2. Mahesh Mehendale
3. Texas Instruments

Bio: Mahesh Mehendale leads the Kilby Labs at Texas Instruments India. His present areas of focus include ultra-low power MCUs. Prior to this, he worked on architectures for low power HD video compression. Since joining TI in 1986, he has led the development of multiple industry leading digital and system-on-a- chip designs including C27x/C28x DSPs (first commercial DSP designed in India) and DM642 digital media processor. In recognition of his technical leadership and high impact innovations, he was elected as TI Fellow in 2003 – first one in TI Asia. Mahesh has done B. Tech (EE, ‘84), M. Tech (CS&E;, ‘86) and Ph.D. (’00) from the Indian Institute of Technology, Bombay. He has published more than 45 papers at international conferences/journals and presented many invited talks/tutorials. He was the general co-chair for the VLSI Design 2010 conference. He has co-authored a book on “VLSI synthesis of DSP kernels” published by Kluwer Academic Publishers and a chapter on “Introduction to SoC” for a book on System on a Package (SOP) published by McGraw-Hill. Mahesh holds 6 US patents and was elected senior member of IEEE in 2000. He received the “Distinguished Alumnus” award from IIT Bombay in March 2012.