Detailed VLSID 2013 conference Program

Main Conference Program: Day 1 (7th January 2013)

Begin Time	End Time	Time	Track A	Track B	Track C	Track S(tudent)	Track E	Track D
7:30 AM	9:00 AM		Registrations
9:00 AM	9:40 AM	Morning	Ganesh Vandana, and Welcome talks
9:45 AM	10:30 AM		Keynote by Abhi Talwalkar, CEO of LSI "Intelligent Silicon in the Data-centric Era"
10:35 AM	11:20 AM		Keynote by Ruchir Puri, Fellow IBM - Opportunities and Challenges for High Performance Microprocessor Deisgns and Design Automation Download
11:25 AM	11:35 AM		Intro to Exhibits
11:35 AM	11:50 PM		Tea/Coffee Break
11:50 PM	1:10 PM	Pre-Lunch	Session A1 Architectural Energy Optimizations - I - Charudhattan Nagarajan, Swaroop Ghosh	Session B1 Analog Techniques - Amit Patra	Session C1 Embedded Architectures- Nitin Chandrachoodan	Session S1 S1.1 Inauguration of Student conf cum Keynote Conference- Dr. Rajat Moona, Director General CDAC, Pune	Session E1 Invited Industry Forum Keynote by T R Ramachandran, VP, CQP LSI, "Green Electronics & Sustainability – Key Business Imperatives for the 21st Century"	Session D1 Invited Speaker - C.Srinivasan, Cosmic Circuits, "Evolution of Mixed Signal Design"
			A1.1 Optimal Pipeline Depth And Supply Voltage For Power-constrained Processors- Abhijit Giri, S. K. Nandy Download	B1.1 PODIA : Power Optimization through Differential Imbalanced Amplifier - Prashant Dubey, Atul Kumar Kashyap, Navneet Gupta, Kaushik Saha	C1.1 MAPro: A Tiny Processor for Reconfigurable Baseband Modulation Mapping - Liang Tang, Jude Angelo Ambrose, Sri Parameswaran Download
			A1.2 CASHIER: A Cache Energy Saving Technique for QoS Systems Sparsh Mittal, Zhao Zhang, Yanan Cao Download	B1.2 A Capacitor-less Low Drop-out (LDO) Regulator with Improved Transient Response for System-on-Chip Applications Cheekala Lovaraju, Ashis Maity, Amit Patra Download	C1.2 A Study on Instruction-set Selection using Multi-application based Application Specific Instruction-set Processors Roshan Ragel, Swarnalatha Radhakrishnan, Jude Angelo Ambrose, Sri Parameswaran Download	S1.2 Product definition- Yatin Acharya, Marvel
			A1.3 Dynamic Cache Tuning for Efficient Memory Based Computing in Multicore Architectures Hadi Hajimiri, Prabhat Mishra, Swarup Bhunia	B1.3 A Sub-1V 32nA Process, Voltage and Temperature Invariant Voltage Reference Circuit Anvesha Amaravati, Maryam Shojaei Baghini	C1.3 Localized Heating for Building Energy Efficiency- Jun Wei Chuah, Chunxiao Li, Anand Raghunathan, Niraj K. Jha Download
1:10 PM	2:10 PM	Lunch
2:20 PM	3:30 PM	Post Lunch	Session A2 Embedded Tutorial - Embedded Security [Organized by Anand Raghunathan] -Srivaths Ravi	Session B2 Test Cost Reduction and Safety- Kewal Saluja	Session C2 Power and Reliability Considerations in System-Level Design - Bishnupriya Bhattacharya, M. Balakrishnan	Session S2 S2.1 Product/SOC architecture and challenges- Mahesh Mehendale, Fellow TI	Session E2 E2.1 Cloud-Aided Silicon Design - A Paradigm Shift- Jai Iyer, SiCAD	Session D2 "User Track-1 - DFT Session Chair: Rajagopalan Srinivasan"
								D2.1 Novel DFT architecture for multi-core SoCs enabling modular IDDQ - Arvind Jain, Pradeep P and Sachin Badole, TI India
			A2.1 Emerging Frontiers in Embedded Security - Mehran Mozaffari Kermani, Meng Zhang, Anand Raghunathan and Niraj Jha	B2.1 Optimum Test Schedule for SoC with Specified Clock Frequencies and Supply Voltages - Vijay Sheshadri, Vishwani D. Agrawal, Prathima Agrawal Download	C2.1 Lifetime Reliability Aware Architectural Adaptation - Thannirmalai Somu Muthukaruppan, Tulika Mitra Download			D2.2 At-Speed Delay Testing of IOs using existing IEEE 1149.1 TAP Architecture - Mudasir Kawoosa and Rajesh Mittal, TI India
			A2.2 Embedded Tutorial - Securing the Smart Grid and Critical Infrastructure - Shantanu Sarkar, Ravishankar K. Iyer, Hui Lin, Z. Kalbarczyk, Catello Di Martino	B2.2 Reducing Test Time of Power Constrained Test by Optimal Selection of Supply Voltage - Praveen Venkataramani, Vishwani D. Agrawal	C2.2 Power Supply Efficiency Aware Server Allocation in Data Centers - Preeti Ranjan Panda, Manoj Jain, Anubha Verma, Dipankar Sarma, Vaidyanathan Srinivasan Download			D2.3 Efficient Test Clocking Structures and Techniques for Transition Fault Testing of SoCs with Multiple Clock Domains - Rajesh Mittal, Prakash Narayanan, Puneet Sabbarwal, Surya Samavedam, Sujit Tikekar and Charles Kurian, Texas Instruments
				B2.3 On Guaranteeing Capture Safety in At-Speed Scan Testing With Broadcast-Scan-Based Test Compression - Kazunari Enokimoto, Xiaoqing Wen, Kohei Miyase, Jiun-Lang Huang, Seiji Kajihara, Laung-Terng Wang	C2.3 Power-Aware Wrappers for Transaction-Level Virtual Prototypes: a Black Box Based Approach - Ons Mbarek, Alain Pegatoquet, Michel Auguin, Houssem Eddine Fathallah Download	S2.2 SOC Design and Verification - Raghunath Tilak, APM	E2.2 "Semiconductor Industry: Market Drivers and Product Realization Challenges- Yamini Kaur, Cadence	D2.4 On-chip LDOBIST for Extremely Low Cost Test of Voltage Regulators in Mixed Signal SOCs with Integrated Power Management - Rajesh Mittal, Puneet Sabbarwal and Harikrishna Parthasarathy, Texas Instruments, India
3:30 PM	3:50 PM	Tea/Coffee Break
3:50 PM	4:20 PM	Formal Inaguration of Conference by Hon. CM of Maharashtra Shri. Prithviraj Chauhan
4:20 PM	5:05 PM	Keynote by Kishore Manghnani, Vice President of Communications and Consumer Business , Marvell, "Semiconductors in Smart Energy Products"
5:05 PM	6:05 PM	Evening	Panel Discussion "Low Power Design: Top down OR Bottom up OR we have squeezed it all?" moderated by Mahesh Mehendale, Fellow TI. ( Panelists: Ghasi Agrawal, Senior Director, Technology and IP, Foundation R&D, LSI; Satish Soman Fellow, APM; Vasantha Erraguntla, Technology Director, Intel; Srinivas Gande, Senior Director, Digital Entertainment Business Unit, Marvell; )
6:05 PM	6:25 PM	Networking Break
6:25 PM	7:45 PM	Evening	Session A3 Architectural Energy Optimizations - II- Rajiv Joshi	Session B3 High Performance Mixed-Signal Design- Tarun K. Bhattacharya	Session C3 Design and Synthesis of Reversible Logic - Siddhartha Duttagupta, Girish J. Pathak	Session S3 SOC backend - Ranjit Yashwante and Jim Monthier, LSI	Session E3 Industry Forum [Panel] “Green technology for electronics in India – opportunity or just another buzzword” -	Session D3 "User Track-2 Pot Pourri (Mixed Signal/Reliability/Design Closure)"
								D3.1 Zero defect Mixed Signal SoCs- Kushal Kamal, Sunny Gupta and Kumar Abhishek, Freescale
			A3.1 A 40nm 650Mhz 0.5fJ/Bit/Search TCAM compiler using Complementary Bit-cell Architecture - Rashmi Sachan, Shahid Ali, Chandan Bist, Sunil Misra, Vinod Menezes, Sharad Gupta,Pat Bosshart	B3.1 Area & Power efficient 3.4Gbps/Channel HDMI Transmitter with Single-Ended Structure - Nitin Gupta, Phalguni Bala, Vijay Kumar Singh Download	C3.1 K-Algorithm: An Improved Booth's Recoding for Optimal Fault-Tolerant Reversible Multiplier - Kartikeya Bhardwaj, Bharat M. Deshpande			D3.2 Test Time Reduction of a Pin Limited Large Hierarchical MultiPower Domain SoC- Ajay Dimri, Rudraksha Dani and Shiv Kumar Vats, STMicroelectronics Ltd
			A3.2 Efficient Window-Architecture Design using Completely Scaling-Free CORDIC Pipeline - Supriya Aggarwal, Kavita Khare	B3.2 Embedded Reconfigurable Augmented DC-DC Boost Converter for Fast Transient Recovery - Neeraj Mishra, Niraj Jha, Santanu Kapat, Amit Patra	C3.2 A Low Power Fault Tolerant Reversible Decoder Using MOS Transistors - Md. Shamsujjoha, Hafiz Md. Hasan Babu Download			D3.3 HoS: A metric driven approach to measure Quality/Health of Silicon- Manish Verma, AnilKumar SeshagiriRao and Shivaprasad Sadashivaiah, Infineon Technologies India Private Limited
			A3.3 Ultralow-Power and Robust Embedded Memory for Bioimplantable Microsystems - MaryamSadat Hashemian, Swarup Bhunia Download	B3.3 Implementation of a Charge Redistribution Based 2-D DCT Architecture for Wireless Capsule Endoscopy - Bhuvanan Kaliannan, Vijaya Sankara Rao Pasupureddi	C3.3 Embedded Tutorial - Applications of Reversible Logic in Cryptography and Coding Theory - Indranil Sengupta, Kamalika Datta Download	S3.2 Panel discussion: Market Survey (understanding need of the end user) Vs. Steve Job's way (telling end user what they need)- Yatin Acharya Marvel, Satish Soman Fellow APM, Mr. Vivek Pawar CEO SankalpSemi, K Gopinath, VP of Engineering at AirTight Networks, Jaya Panwalkar Sr. Director NVIDIA		D3.4 Do-Different design closure techniques for multimedia application processor System-On-Chip for wireless, Mobile Internet Device and consumer market- Naishad Parikh, Vivek Pai, Anubhav Shukla, Sharad Arora and Ajay Shah, Texas Instruments

Main Conference Program: Day 2 (8th January 2013)

Begin Time

End Time

Time

Track A

Track B

Track C

Track S(tudent)

Track E

Track D

9:00 AM

9:45 AM

Morning

Keynote by Dr. Paramesh Gopi - Cloud computing needs at less power and low cost and Mr. Amal Bommireddy - Challenges of First pass Silicon

9:50 AM10:35 AM

Keynote by Lou Scheffer, Howard Hughes Medical Institute - Deciphering the brain, cousin to the chip
Download

10:35 AM

10:55 AM

Tea/Coffee Break

11:00 AM

12:20 PM

Pre-Lunch

Session A4

Clock Related Circuits-
Saibal Mukhopadhyay,
Rahul Rao

Session B4

High Performance RF-
Harish Krishnaswamy

Session C4

Embedded Tutorial - Power Efficient Protection from Soft Errors-
Kyoungwoo Lee, Reiley Jeyapaul

Download

Session S4

S4.1

Board/System Design challenges -

Jim Monthie, LSI

Session E4

E4.1

"Industry
Forum Invited Talk"-

Amit Merchant, IBM, "Smarter Cities"

Download

Session D4

Invited Speaker - Satish Soman
"Global Design Closure"

A4.1
A 50nW, 100kbps Clock/Data Recovery Circuit in an FSK RF Receiver on a Body Sensor Node -
Aatmesh Shrivastava, Jagdish Pandey, Brian Otis, Benton H. Calhoun

Download

B4.1
A Fully Integrated CMOS Class-E Power Amplifier for Reconfigurable Transmitters with WCDMA/WiMAX applications -
HyukSu Son, Woo Young Kim, Joo Young Jang, Hae Jin Lee, Inn Yeal Oh, Chul Soon Park

A4.2
A Novel Scheme to Reset Through Clock -
Sanku Mukherjee, M thrivikraman, Anil Goyal, Arul Sendhil

Download

B4.2

A 140iA 34ppm/°C 30MHz clock oscillator in 28nm CMOS bulk process-

Abhirup Lahiri, Anurag Tiwari

Download

S4.2
System SW and Application SW -

Himanshu Bhat NVIDIA

E4.2

"Accelerating Innovation in Verification Productivity"-

Harish Balan, Sr. Director, Synopsys

A4.3
Impact of Clock-Gating on Power Distribution Network using Wavelet Analysis-
Vinay C Patil, Sudarshan Srinivasan, Wayne P. Burleson, Sandip Kundu

Download

B4.3
A 44 GHz Quadrature Traveling Wave Oscillator-
Somnath Kundu, Shouri Chatterjee

Download

12:20 PM

1:20 PM

Lunch

1:20 PM

2:40 PM

Post Lunch

Session A5

Embedded Tutorial- Emerging Computing Technologies -

Saibal Mukhopadhyay, Abhijit Chatterjee

Session B5

RF Oscillators and VCOs-

Aniruddhan Sankaran

Session C5

MEMS and Memristors: Design, Modeling and Testing-
Girish J. Pathak, Siddhartha Duttagupta

Session S5

S5.1

Product/SW Testing -

Milind Sinkar, Abhijeet Aphale, LSI

Session E5

E5.1

Presentation by Madhu Lakshmanan, Sr. Manager, Qlogic, "High Performance Data Networking Technologies"

E5.1

Presentation by Pradeep Vajram, CEO, Smartplay, "SoC Design Services: A Growth Driver in Indian Ecosystem"

E5.3

Presentation Narasimhan Parthasarathy: “Rambus – A company of Inventors”

Session D5

"User Track - 3
System-level Design/ESL"
Session Chair:
Srini Venkataramanan

D5.1
A modular approach for achieving SOC level Gate simulation verification-
Sundeep Gupta, Shriprasad Lokare, Applied Micro

A5.1
Prospects of Near-Threshold Voltage Design for Green Computing-
Surhud Khare, Shailendra Jain

Download

B5.1
38dB Tuning Range Coupled VCO based Divider Architecture with 68uW power @2.0 GHz in 65nm CMOS-
Prashant Dubey, Rashmi Agarwal

C5.1
Microelectromechanical Longitudinal Resonator for Frequency Reference Applications-
Ritesh Ray Chaudhuri, Tarun Kanti Bhattacharyya

D5.2
Clock Abstraction & Event Synchronization For Infiniband Mutli lane Link-Layer Using Transaction Level Modeling-
Chaitanya Naik and Himanshu Rawal, Intel India Pvt Ltd

A5.2
Can Silicon machines match the efficiency of the human brain-
Bipin Rajendran

B5.2
A Wide Range CMOS VCO for PLL Applications-
Amiya Prasad Behera, Subhasis Sasmal, Prajit Nandi

C5.2
Design and simulation of structurally decoupled 4-DOF MEMS vibratory gyroscope-
Ankush Jain, Ram Gopal

D5.3
System Verilog DPI Based SOC simulation environment reuse for Verification, Validation and FPGA
Nisreen Taiyeby, Pushkar Naik, Shailendra Chavan, Jayant Kurkure. Applied Micro

A5.3
Emerging Memory Technologies: What it means for Computer System Designers-
Moin Qureshi

B5.3
Empty Slot

C5.3
Sneak-path Testing of Memristor-based Memories-
Sachhidh Kannan, Jeyavijayan Rajendran, Ramesh Karri, Ozgur Sinanoglu

S5.2

Taking the product to Market-

Vivek Tyagi, Freescale

D5.4
Virtual Platforms for System Debugging and Analysis-
Praveen Wadikar, Cadence Design Systems

2:40 PM

3:00 PM

Tea/Coffee Break

3:00 PM

4:20 PM

Post
Afternoon
Tea

Session A6

Embedded Tutorial - Low Power Computing - Reducing the gap between the Physical and Practical Limits-
Saibal Mukhopadhyay and Sudhakar Yalamanchili, Georgia Institute of Technology

Session B6

Advanced Fault Models and Test Generation-

Anand Bhat

Session C6

Embedded Systems-
Anand Raghunathan, Niraj Jha

Session S6

S6.1

Job opportunities for fresher in Semiconductor industry and required Soft skills -

Pradeep Vajram, CEO, Smartplay

Session E6

Panel Discussion "(Why) Should you do your next Semiconductor, EDA, Systems start-up in India?" Representation by Parag Nayak, CTO, Sankhya labs (Semiconductors), 2) R. K. Patil, CEO, Vayavya (Embedded SW)

Session D6

"User Track-4 - Functional Verification"-
Session Chair: Shankar Hemmady

D6.1
UVM and Integration of Legacy Methodologies-
Amit Sharma and Santosh Sarma, Synopsys India

A6.1
Ultra Low Voltage Spin Devices for Non-Boolean/Neuromorphic Computing-
Kaushik Roy

B6.1
Physics based Fault Models for Testing High-Voltage LDMOS- Sukeshwar Kannan, Bruce Kim, Friedrich Taenzler, Richard Antley, Ken Moushegian, Anurag Gupta

C6.1
Prediction Schemes for Compensating Variable Delay for Improving Performance of Real-Time Control Tasks-
Saptarshi Roy, Amit Patra, Partha P. Chakrabarti, Purnendu Sinha, Dipankar Das

Download

D6.2
Next Generation Verification Approach - OVM-VMM Interoperability-
Vignesh Manoharan, Cypress Semiconductors

A6.2
Future of energy efficient computing by dynamic variation tolerant circuits-
Tanay Karnik

B6.2
Observability-aware Directed Test Generation for Soft Errors and Crosstalk Faults-
Kanad Basu, Prabhat Mishra, Priyadarsan Patra

C6.2
Scheduling Aperiodic Tasks in Next Generation Embedded RealTime Systems-
Rehan Ahmed, Parameshwaram Ramanathan, Kewal K. Saluja, Chunhua Yao

D6.3
Addressing IP Integration Challenges at Functional Verification Level-
Pusuluri Venkata Giri Kumar, Kamlesh Ram Raiter, Devashish Dutta, Naveen Kumar Korada and Spurthi B, Synopsys India Pvt Ltd

A6.3
Architectural Alternatives for Energy Efficient Performance Scaling-
Sudhakar Yalamanchaili

Download

B6.3
At-speed I/O test for fast Vref optimization in high speed single-ended memory systems-
Sanku Mukherjee, Srinivasaraman Chandrasekaran, Ganapathy Subramanyan, Arul Sendhil

Download

C6.3
Energy-efficient and Secure Sensor Data Transmission Using Encompression-
Meng Zhang, Mehran Mozaffari Kermani, Anand Raghunathan, Niraj K. Jha

S6.2

Panel discussion : After Bachelor degree taking Job Vs Higher studies Vs Starting something on our own-

Raman Santhanakrishnan, MD LSI, Pradeep Dharane MD APM, Vivek Pawar CEO Sankalp, Ashutosh Parasnis MD- QLogic, Abhijit Athavale CEO Markonix, Rony Anthony, LSI

D6.4
Accelerating CDC Verification with SDC setup-
Ashish Hari and Yogesh Badaya, Mentor Graphics

4:20 PM

4:35 PM

Networking Break

4:35 PM

5:20 PM

Keynote by Vivek Singh,Intel Fellow, Technology and Manufacturing Group, "Duniyaa Maange Moore!"

5:20 PM

6:20 PM

Evening

Plenary Panel Discussion: “Expectations of Manufacturing Sector from Semiconductor and Embedded System Companies” moderated by
Dr Vinay Vaidya – CTO KPIT Cummins

(Panelists: Madhuri Marathe, TCS; Mr. Amar Variawa, GM – John Deere India; Mr.Sreekumar Panicker – Head Embedded Systems and Software, Eaton; Mr.Pankaj Sonalkar, CEO & Managing Director at Mahindra Navistar Engines Pvt Ltd Pune;Mr. Vivek Tyagi Country Manager- Sales & Marketing at Freescale Semiconductors Inc)

6:30 PM

8:00 PM

Talk by Dr. Vishwani D Agrawal, Chair Auburn University, USA; followed by Awards Ceremony and Cultural Program

8:15 PM

9:55 PM

Banquet Dinner

Main Conference Program: Day 3 (9th January 2013)

Begin Time

End Time

Time

Track A

Track B

Track C

Track D

9:00 AM

9:45 AM

Morning

Keynote by Vijaykrishnan Narayanan, Penn State University - Embedded Vision Systems
Download

9:50 AM10:35 AM

Keynote by Venkat Rajaraman, Solaris - Electronics Backbone of Renewable Energy Industry
Download

10:35 AM

10:55 AM

Tea/Coffee Break

11:00 AM

12:20 PM

Pre-Lunch

Session A7 Embedded Tutorial- Shockproof Your Designs Against ESD Events- [Organized by Nagaraj NS, University of Texas at Dallas]- Nagaraj NS, Arvind NV	Session B7 RF Applications- Harish Krishnaswamy	Session C7 Advances in Functional Verification- Dhiraj Goswami	Session D7 User Track-5 - Physical Design Closure
A7.1 Silicon Technology Impact on ESD Qualification- Charvaka Duvvury Download	B7.1 Multiphase technique to speed-up delay measurement via sub-sampling- Rajath Vasudevamurthy, Bharadwaj Amrutur	C7.1 Assertion-Based Functional Consistency Checking between TLM and RTL Models- Mingsong Chen, Prabhat Mishra Download	D7.1 Staircase non-rectangular macros and related design challenges- Adarsh Subramanya, Gary Gorman and Daniel Lewis, IBM Processor Division, India
	B7.2 Gain, NF and IIP3 Budgeting of LTE Receiver Front End- Vinay M. M., Roy Paily, Anil Mahanta	C7.2 Formal Verification of Hardware / Software Power Management Strategies- Rajdeep Mukherjee, Pallab Dasgupta, Ajit Pal, Subhankar Mukherjee Download	D7.2 Optimal Placement of Spare Flip Flop circuitry in high performance processors- Ayan Datta, Charudhattan Nagarajan, Vijay K Ankenapalli and Sumitha George, IBM India
A7.2 Comprehensive Layout-based ESD Check Methodology with Fast Full-chip Static and Maco-level Dynamic Solutions- Norman Chang, Ting-Sheng Ku, Jai Pollayil Download	B7.3 Adaptive RF Front-end Design Via Self-discovery: Using Real-time Data to Optimize Adaptation Control- Debashis Banerjee, Aritra Banerjee, Abhijit Chatterjee	C7.3 Short Paper - Model Checking Controllers with Predicate Inputs- Santhosh Prabhu M, Pallab Dasgupta Download	D7.3 Using fast, high-capacity, attofarad-accurate 3D extraction for successful design of high performance IPs in advanced CMOS nodes- Atul Bhargava, Srisurya Konduri, Chittoor Parthasarthy, Jean Claude Marin and Claudia Relyea, STMicroelectronics, India
		C7.4 Short Paper - Verification of KPN level Transformations- Chandan Karfa, Dipankar Sarkar, Chittaranjan Mandal Download	D7.4 Impact of Package and On-Die Power Distribution Network on the relative performance of individual Cores in a multi-Core SoC- Kannan N and Gagan Kumar, Freescale

12:20 PM

1:20 PM

Lunch

1:20 PM

2:40 PM

Post Lunch

Session A8 Analog and Digital Error Correction- Madhav Desai	Session B8 FPGA Implementation- Shankar Balachandran	Session C8 Logic Synthesis and Physical Design- Yamini Kaur	Session D8 User Track-6 - Pot Pourri (Low Power, Power Integrity, STA) Session Chair: Yash Punati
A8.1 Design of a Fault Tolerant Reversible Compact Unidirectional Barrel Shifter- Md. Shamsujjoha, Hafiz Md. Hasan Babu, Lafifa Jamal, Ahsan Raja Chowdhury	B8.1 Design and Implementation of a High Speed MAP Decoder Architecture for Turbo Decoding- Rahul Shrestha, Roy Paily Download	C8.1 Measuring Area-Complexity Using Boolean Difference- Ankit Kagliwal, Shankar Balachandran Download	D8.1 Validation and Debugging Techniques for Statistical Timing Analysis- Sachin Shrivastava, Cadence Design Systems
A8.2 A High Throughput Multiplier Design Exploiting Input Based Statistical Distribution In Completion Delays- Ravi Tej Uppu, Ravi Kanth Uppu, Adit Singh, Abhjijit Chatterjee	B8.2 Accelerating 3D-FFT using Hard Embedded Blocks in FPGAs- B. Sharat Chandra Varma, Kolin Paul, M. Balakrishnan Download	C8.2 Polynomial Complexity Asynchronous Control Circuit Synthesis of Concurrent Specifications based on Burst-Mode FSM Decomposition- Pavlos M. Mattheakis, Christos P. Sotiriou	D8.2 A Case-study of Production Debug of At-Speed Silicon Failures Using Low Power ATPG Techniques- Nayana Prakash, Sanjay HV, Venkatraman Ramakrishnan, Srivaths Ravi and Krishna Chakravadhanula, Texas Instruments, India
A8.3 Input Referred Offset reduction in Very High Speed Differential Receivers- Rajat Chauhan, Manigandan Selvam Download	B8.3 VLSI Implementation of Enhanced Edge Preserving Impulse Noise Removal Technique- Deepa P., Vasanthanayaki. C.	C8.3 Short Paper - Geometry Independent Wirelength Estimation Method in VLSI Routing- Raka Sardar, Ratna Mondal, Tuhina Samanta	D8.3 EDA Challenges in Utilizing AOCV STA to Minimize Design Margins for Signoff and Optimization- Sreeram Chandrasekar, Sourav Banerjee and Nagabharana Teeka, Texas Instruments India
		C8.4 Short Paper - Impact of Power Supply Noise on Clock Jitter in High-Speed DDR Memory Interfaces- Jim Monthie,Vineet Sreekumar, Ranjit Yashwante Download	D8.4 Energy Estimation at multiple abstraction levels in a wireless baseband processor design- Prabhat Avasare and Martin Palkovic, IMEC, Belgium

2:40 PM

3:00 PM

Tea/Coffee Break

3:00 PM

3:45 PM

Keynote by Ken Chang, Xilinx -Advancing High Performance System-on-Package via Heterogeneous 3-D Integration

3:45 PM

4:05

Networking Break

4:05 PM

5:25 PM

Post
Afternoon
Tea

Session A9 Post Silicon Validation- Shridhar G. Bendi	Session B9 Mixed Signal Techniques- Amit Patra	Session C9 Advances in Circuit Simulation, Analysis and Design- Bipin Rajendran	Session D9 User Track-7 - Design Methodologies and Tool Flows- Session Chair: Jayendra Dwaraka
	Session B9 Mixed Signal Techniques- Amit Patra		D9.1 100Gb Ethernet Tributary Interface Module Card for OTN DWDM platform, From Concept to Production- Kiran Kapshikar, Manish Verma, Ravi Tangirala and Tulasi Veguru, Infinera
A9.1 Dynamic Trace Signal Selection for Post-Silicon Validation Kihyuk Han, Joon-Sung Yang, Jacob A. Abraham	B9.1 Design and Implementation of a High-Speed, Power-Efficient, Modified Hybrid-Mode Sense Amplifier for SRAM Applications- Debajit Bhattacharya, Ashis Maity, Amit Patra Download	C9.1 Hardware-corroborated Variability-Aware SRAM Methodology- Rajiv Joshi, Rouwaida Kanj, Shahid Butt, Emrah Acar, Dallas Lea, Dean Sciacca	D9.2 Zero Simulation Verification Flow For SOC Using Formal Verification Techniques- Garima Srivastava, Kushagra Garg, Subir Roy, Debmalya Lahiri and Bijitendra Mittra, Texas Instruments
A9.2 Efficient Signal Selection using Fine-grained Combination of Scan and Trace Buffers- Kamran Rahmani, Prabhat Mishra	B9.2 A Feed-Forward Equalizer for Capacitively Coupled On-Chip Interconnect- K. Naveen, Marshnil Dave, Maryam Shojaei Baghini, Dinesh K. Sharma Download	C9.2 FinPrin: Analysis and Optimization of FinFET Logic Circuits under PVT Variations- Yang Yang, Niraj K. Jha	D9.3 SCONE – Smaller Cone debugging technique based on divide and conquer to diagnose complex failures in equivalency check- Aman Jain, LSI India
A9.3 VAST: Post-Silicon VAlidation and Diagnosis of RF/Mixed-Signal Circuits Using Signature Tests- Sabyasachi Deyati, Aritra Banerjee , Barry John Muldrey, Abhijit Chatterjee Download	B9.3 Two-Path Quadrature Cascaded Band-Pass Sigma-Delta Modulators- Nithin Kumar Y.B., Edoardo Bonizzoni, Amit Patra, Franco Maloberti Download	C9.3 Memory Efficient implementation of Two Graph based Circuit Simulator for PDE-Electrical Analogy- Yogesh Dilip Save, H. Narayanan, Sachin B. Patkar Download	D9.4 Custom Datapath Synthesis Methodology for High-Speed Microprocessor Design- Sourav Saha and Charudhattan Nagarajan, IBM Processor Division, India