Abstract :- This talk will focus on the evolution of Mixed signal design in DSM. As the process features shrink, some of the aspects of mixed signal designs have become easier and some harder.

The evolution of architectures in data converters, PLLs, Power circuits , connectivity etc will be highlighted with focus on the digitally assisted analog circuits. The availability of high BW xtors albeit at lower voltages tolerances help tradeoff accuracy and speed. Architectures that take advantage of these will be touched upon. Concerns on reliability and techniques to address some of these will be addressed.

Speaker Biography :- C.Srinivasan received his B.Tech in Electronics and Communications from IIT Chennai in 1989 and M.S from IIT Chennai in 1996. His work experience includes setting up a Startup, Cosmic Circuits, 14 years in TI in the mixed signal design group and 1.5 years in HCL Technologies working on board level solutions. In his 14 years of association with TI, he worked in a variety of fields. Starting with Analog modeling, he then led a team to develop data converters. His team was responsible to putting TI in a leadership position on the SAR ADC products with resolutions up to 18bits and speeds up to 1MSPS. Subsequently he led a team to develop WLAN chips. His team was responsible for the full digital implementation of the PHY and MAC layers as well as communication algorithm development.

In 2005, he co-founded Cosmic Circuits focusing on Analog and Mixed Signal designs. As VP Engineering, he has setup the team to execute a variety of analog IPs including Power Managements chips, Data Converters, Analog Front Ends, PLLs, Serial Interfaces, Analog ASICs etc. He has authored 3 international papers and 5 patents in his name.

Novel DFT architecture for multi-core SoCs enabling modular IDDQ
Arvind Jain, Pradeep P and Sachin Badole, TI India

Test Time Reduction of a Pin Limited Large Hierarchical MultiPower Domain SoC Architecture
Ajay Dimri, Rudraksha Dani and Shiv Kumar Vats,
ST Microelectronics Ltd

At-Speed Delay Testing of IOs using existing IEEE 1149.1 TAP Architecture
Mudasir Kawoosa and Rajesh Mittal, TI India

Efficient Test Clocking Structures and Techniques for Transition Fault Testing of SoCs with Multiple Clock Domains
Rajesh Mittal, Prakash Narayanan, Puneet Sabbarwal, Surya Samavedam, Sujit Tikekar and Charles Kurian, Texas Instruments

Abstract :- Today’s SoC designs integrate complex heterogeneous IPs/Subsystems. These IPs are concurrently developed in different geographies. Physical design issues ( like congestion etc) of these complex IPs ( and their interactions) many times remain latent till final SoC enters physical design cycle. Late discovery of these issues causes long and unpredictable iterations in the physical design of the IP as well as SoC. This talk provides further insight into the nature of this problem and requirements of solutions. Current approaches in the industry are also discussed.

Speaker Biography :- Satish has over 30 years of experience in Chips and System Design. His expertise spans Architecture, Logic Design, Verification, Validation and field support of ASIC/COT designs. He has successfully delivered 18 production designs in the areas of Computing, Multimedia and Networking domains. He has held executive management positions at DEC, LSI Logic, Axiowave and Lucent. He was co-founder of Nexabit (acquired by Lucent). He is also on advisory boards of few start-up companies. Satish holds 16 patents. He has published papers in leading technical journals and conferences
He holds MS in Computer Engineering from Syracuse University and B.Tech in Electrical Engineering from IIT-Bombay